Electric breakdown in MOS devices is a well recognized problem. The breakdown phenomena escalates when the space between the source and drain region continues to narrow in MOS transistors made by advanced processing technology, stemming from increased electric fields in the channel region. As appreciated by those skilled in the art, the mechanism of the breakdown phenomena in a MOS transistor includes junction breakdown, punchthrough breakdown and snapback breakdown. Junction breakdown occurs due to abrupt doping profile changes between the highly doped N+ drain region and P type substrate, and can be prevented, for example, by forming an NMOS device on a lightly doped P type substrate. Punchthrough breakdown happens when the drain and source depletion regions meet under the channel when the reverse-bias voltage on the drain/substrate junction is increased. In the case of an NMOS transistor, punchthrough breakdown can be suppressed by local implant (halo implant) of highly concentrated P-type impurity deep under the channel region on the side wall of the N+ drain/P-substrate, N+ source/P-substrate junctions. Snapback breakdown in an NMOS transistor occurs near the drain region during saturated operation (transistor is turned on). When a voltage is applied on the drain, a lateral electric field is presented in the channel region of the transistor and the peak electric field occurs near the drain region. The high electric field accelerates the electrons in the channel region and causes the electrons to gain enough kinetic energy to become “hot” near the edge of the N+ drain region. The “hot” electrons cause impact ionization of materials near the drain edge and create electron-hole pairs. Electrons will inject into the gate oxide due to positive bias on the gate electrode, while holes inject into the substrate. Some of these holes are collected by the source and this hole current positively biases the substrate/source junction, which in turn causes more electrons being pulled out from the source region, accelerated and injected into the drain region. These electrons, in turn, cause more impact ionization near the drain and create more electron-hole pairs. When this positive-feedback mechanism starts in the substrate, the substrate acts much like an NPN BJT device working under forward-active mode, where the forward biased substrate-to-source junction (base-to-emitter junction) causes large current to be injected into the P-type substrate (base). The current is amplified in the substrate region (base) and collected by the drain (collector) through the reverse biased drain-to-substrate junction (collector-to-base junction). Snapback breakdown is a type of avalanche breakdown. When it happens in a MOS device, large current is created in the substrate and voltage applied on the gate electrode loses control over the current flow in the channel region, which causes a MOS device stop to functioning. Furthermore, the electrons injected into the gate oxide may cause negative effects, such as Vt shift and reliability degradation, among others. Under severe situations, snapback breakdown may cause permanent physical damage in the gate oxide.
FIG. 1A shows a section view of a prior art high voltage MOS (HVMOS) transistor 10. Transistor 10 has a typical structure of a lateral power MOSFET for high-voltage applications, namely for the automobile industry, portable telecommunication devices, medical equipment, display drivers, and other areas which call for high reliability and compactness. In transistor 10, a lightly doped N− region 12 is formed as an extension of the highly doped N+ drain region 14 of an NMOS transistor. The lightly doped N− region 12 is called N-extension region or N-drift region. The N-extension region 12 formed between the P-type channel and the N+ drain region 14 results in a more graded N-type impurity profile, which improves the drain-to-substrate junction breakdown voltage under the N+ drain area. Thick field oxide 11 is formed over N-extension region 12 and a portion of gate 13 is formed along the upper edge of thick field oxide 11. The thick field oxide 11 is applied to protect the gate 13 from high electrical field on the drain side, which causes “hot carrier” injection into the gate oxide 15. The N-extension region 12 under field oxide 11 between the N+ drain and gate 13 will absorb some voltage applied on the drain when the device is under saturated operation (device is ON) and reduce the peak electric field near the N+ drain edge. This, in turn, will improve the snapback breakdown (on-breakdown) voltage near the drain edge. However, the thick field oxide 11 of this prior art structure causes the transistor 10 to have undesirably large device dimensions, which makes HVMOS devices with this type of structure unfavorable for being integrated with low voltage MOS (LVMOS) devices of small device dimensions on a same chip, as required by many applications.
FIG. 1B illustrates the structure of another previously known HVMOS transistor 20, which is integrated with its low voltage counterparts on a same substrate for HV applications such as source driver of LCD monitors, among others. This prior art structure includes an N-extension region 21A on the source side and an N− extension region 21B on the drain side. The double-diffused drain and source region of this prior art structure reduce the peak electric field in the channel region, and in turn, can sustain higher Vd applied on the drain 24. Transistor 20 also includes a thick gate dielectric 25 which is about four to five times thicker than that of a low voltage MOS transistor (LVMOS), in order to sustain higher Vg applied on gate electrode 23. However, further HV applications push the supply voltages of current on-chip HVMOS devices to even higher limit, which demands improved on-breakdown voltages in existing on-chip HVMOS devices, due to increased electric field in the conducting channel.
Shown in FIG. 1C is a widely recognized structure of a low voltage short channel NMOS transistor 30, which reduces snapback breakdown near the drain 34 edge by forming a lightly doped N-section 35 of the drain (LDD) at the edge near the channel. The LDD region 35 between the channel and the N+ drain region 34 absorbs some of the voltage applied on the drain when the device is in operational mode and attenuates the electric field near the N+ drain edge to a value below the critical ionization field, which, in turn, reduces “hot carrier” injection into the gate oxide. However, as recognized by those skilled in the art, as MOS transistor channel spacing decreases, the peak electric field at the N+ drain edge increases significantly. Therefore, the LDD technique will reach its own limit where the peak electric field at the N+ drain edge exceeds the critical value and triggers the catastrophic avalanche breakdown.
In view of these and other problems in the prior efforts to reduce the on-breakdown and suppress the on-breakdown effects, there is a need for improved or new MOS transistor structures, which improve on-breakdown voltage and reduce “hot-carrier” degradation, and methods of fabricating the same, in order to cope with the continuing scaling down of device dimensions.